Layout Driven Logic Synthesis and Optimization techniques for FPGA
نویسندگان
چکیده
منابع مشابه
Layout driven FPGA packing algorithm for performance optimization
FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, b...
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With the advent of deep sub-microntechnologies,interconnectloads and delays are becoming dominant. Consequently, the currently used design ow of iterativelyperforming logic synthesis with statistical wire-load models, doing placement & routing, extracting par-asitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the ...
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